How to Tape Out Your First ASIC Without a Foundry Account

Short answer: You can tape out a first ASIC without holding a direct foundry account by working through an authorized MPW, design-enablement or aggregation provider that manages the commercial and manufacturing interface. This does not bypass foundry requirements. Your organization may still need eligibility and export-control review, an NDA or design-kit licence agreement, controlled PDK access, an approved EDA/signoff flow, design registration, quotation and purchase order, followed by provider acceptance of the final GDS/OASIS package. Start with a non-confidential route review; obtain written provider confirmation before treating any process, run or date as available.

A “foundry account” can mean several things: a commercial customer relationship, access to secure technical portals, a PDK licence, permission to register a design, or authority to place manufacturing orders. A service provider can coordinate some or all of these layers, but no legitimate route makes identity, licensing, technical acceptance or compliance disappear.

What the provider actually changes

A direct foundry relationship asks a new design team to navigate account onboarding, commercial terms, technical enablement and manufacturing operations. An MPW provider or aggregator can provide a defined customer interface, combine designs for a shared run, distribute controlled documentation, review the handoff and coordinate downstream activities. The foundry remains responsible for its manufacturing acceptance and milestones; the design team remains responsible for design intent and the agreed signoff scope.

A practical onboarding sequence

1. Define a non-confidential project identity

State who the contracting entity is, where the design and end use are located, the high-level application, the target process family, the estimated area, the design stage and the desired delivery form. If a university program, subsidized price or open-source run is involved, establish whether its participation conditions match your project.

2. Complete eligibility and export-control screening

Programs may require registration in advance of a run deadline, and some publish a distinct export-control information deadline. A provider cannot promise participation before the applicable review. Missing or inconsistent entity, destination or end-use information can stop the route even when the circuit is technically suitable.

3. Execute the correct NDA and licence path

Commercial PDKs and rule decks are usually controlled. The relevant agreement may be an NDA, a design-kit licence agreement, program participation terms or a combination. Confirm which organization and individual users are covered, what environment is permitted, and how version updates or access termination are handled.

4. Obtain and freeze the implementation environment

Record the PDK release, technology option, supported EDA versions, standard-cell or analog IP releases, model corners, rule decks and signoff expectations. “We have a 55 nm PDK” is not a sufficient configuration record. The exact process option and version must match the route that will accept the design.

5. Register the design before the named deadline

Some published dates are registration deadlines; others are final GDS submission or tapeout dates. The provider may require an area estimate, signed quote, purchase order or dry-run data before final delivery. Record the date, timezone, milestone definition and last permitted change to area or option.

6. Complete design and signoff with owned evidence

Keep evidence for functional verification, timing, analog corners, DRC, LVS, ERC, antenna, density, latch-up, ESD, power integrity, reliability assumptions and any accepted waivers that apply to the design. Provider checks do not replace the design owner’s verification responsibility.

7. Release one controlled final-data package

The release package normally identifies the top cell, units, process/option, layer-map reference, checksum, signoff status, known waivers, area and owner. GDS or OASIS is not “final” because a file transfer completed; it is final when the design team has approved a controlled revision and the provider accepts the applicable data gates.

8. Separate run milestones from post-fab delivery

Run tapeout, mask release, wafer start, FAB Out, wafer probe, dicing, package assembly, final test and shipment are different states. Ask which are visible and which party owns each transition. A foundry account is not the main question once the project reaches this stage; the delivery contract and evidence chain are.

The minimum evidence package before you commit

Three account-access mistakes to avoid

Mistake 1: treating an online PDK as authorization for a commercial run. An open or educational design kit can be valuable, but run participation, design rules, support, IP and commercial manufacturing terms remain programme-specific.

Mistake 2: choosing a calendar row before the technology option. A node family can contain multiple voltage, RF, eNVM, BCD, metal and device configurations. A run date for the wrong option has no project value.

Mistake 3: asking a public form to carry design IP. The public intake is only for high-level screening. Confidential exchange must wait for an authorized channel, access controls and a named recipient. MST’s public intake does not request GDS/OASIS, RTL, netlists, schematics, layouts, PDK/rule files or proprietary IP.

When a direct foundry relationship may become appropriate

A direct or dedicated commercial route becomes more relevant when wafer volume, long-term supply, process customisation, manufacturing change control, yield learning, quality systems or product qualification require it. A provider-led first tapeout can still be useful, but the team should ask early how a successful prototype transitions to a dedicated lot or production arrangement.

Use the MPW RFQ Pack builder for a non-confidential intake outline and read the MST MPW access guide. Compare route economics in Where Can I Manufacture a Small Batch of Custom Chips?, select milestones with How to Choose an MPW Shuttle Run, and align the physical delivery in Small-Batch Chip Manufacturing: Process, PDK, Packaging and Test. The existing final GDS to first-silicon checklist explains the later release chain.

Request a non-confidential first-ASIC access review. MST can help structure the requirement and coordinate a reviewed provider path; access, technical acceptance, capacity, quotation and dates remain provider-confirmed.

Frequently asked questions

Can an individual order a custom ASIC from a foundry?

Some programs accept projects only from eligible organizations or through defined providers, and commercial/legal requirements vary. Start by identifying a valid contracting entity and the provider’s access route rather than assuming a consumer-style individual order.

Can a service provider give me a foundry PDK?

An authorized provider may coordinate controlled PDK access under the relevant NDA or licence. It cannot legitimately redistribute confidential design-kit material outside those terms. Confirm the exact process, version, permitted users and access environment.

Does using an MPW provider guarantee foundry acceptance?

No. The provider can screen, coordinate and prepare the path, but entity eligibility, process fit, data quality, commercial approval, capacity and manufacturing acceptance still have gates. Keep every preliminary result labelled as preliminary fit until written confirmation.

Can I reserve a run before my layout is finished?

Some programs register area before final GDS, often with commercial and technical prerequisites. The allowed area change and final-data window are program-specific, so record both milestones and the provider’s cancellation or movement rules.

Who owns the chip design when a provider coordinates tapeout?

Ownership and licence rights come from the signed agreements, not from the word “MPW.” Review design IP, third-party IP, mask/data rights, permitted use and confidentiality terms with qualified counsel before exchanging controlled material.

Primary sources and review boundary

• EUROPRACTICE 2026 schedules and prices — examples of registration, export-control, final-data, price and eligibility conditions.
• GlobalFoundries process design kits — official description of PDK components and supported design enablement.
• GlobalFoundries Value Added Partner Program — an official example of partner-based design enablement and services.
• imec IC-Link 2026 MPW schedules — provider-facing schedules and named run milestones.
• imec IC-Link TSMC University FinFET Program — an example of eligibility-specific access through a program provider.

Last technically reviewed: July 30, 2026. This guide does not grant PDK access or establish legal, export-control or manufacturing eligibility. Agreements, access conditions, process options, run capacity and milestones require current provider confirmation and appropriate professional review.