MPW Packaging and Test Tutorial: Plan Your First Silicon

Short answer: plan MPW packaging and test before final layout release. Define whether you need wafers, bare die or packaged units; how electrical screening will work; how the die connects to the package and board; and which measurements make a sample useful. A fabrication deliverable is not automatically a tested, board-ready chip.

This tutorial produces a first-silicon sample plan. It is intended for a team preparing its first evaluation, with package and test details confirmed by the responsible engineering partners.

Step 1: distinguish the post-wafer stages

Wafer probe or wafer sort

Electrical measurements on die before singulation, where included in the program. Define the probe arrangement, tests and data required.

Dicing and die handling

Separating and identifying samples while preserving orientation and traceability.

Assembly or packaging

Connecting and protecting the die in the selected package or assembly arrangement.

Packaged-device test and characterization

Checking the assembled sample, then measuring the behavior needed for the engineering evaluation. These scopes should be defined separately.

EUROPRACTICE explicitly distinguishes its usual un-packaged, untested prototypes from optional downstream services. Its ASIC packaging documentation describes packaging choices and practical assembly inputs. Confirm the deliverable for your own route.

Step 2: prepare the die-to-package connection record

Before treating a package family as selected, bring the assembler a controlled die outline, pad map and proposed pin assignment through the approved data path. Record dimensions and units, pad identities and coordinates, orientation/view convention, power and ground assignments, and any special connection needs.

A pad number, package pin number and board net name are three different identifiers. Put their mapping in one revision-controlled record. Ask the assembler to review die fit and connection feasibility; the package’s pin count alone is not enough.

Try the Package & Assembly Selector to organize candidate families and questions. It is a planning aid, not a bonding-feasibility or electrical-signoff result.

Step 3: work backward from the desired samples

Suppose an invented project wants 20 packaged evaluation units: 12 for measurements, four for board development and four retained as spares. That allocation describes a desired outcome. The actual delivered quantity depends on the agreed route, screening, assembly and test results.

1. Ask what die allocation the shuttle actually supplies.
2. Confirm whether probe is included and how die are selected for assembly.
3. Agree how many die enter assembly and how assembly or test losses are handled commercially.
4. Specify what “delivered unit” means: assembled only, electrically screened, or characterized against a named test plan.
5. Keep a reserve/rework decision explicit instead of assuming every fabricated die becomes a usable sample.

Track quantities at each stage. Die allocated, die probed, die assembled, devices passing a stated screen and devices shipped are different counts.

Step 4: write the first-silicon test plan

For each intended measurement, record the sample identifier, board/fixture revision, instruments, design-approved operating conditions, procedure, expected behavior, pass/fail criterion and stored output. Put limits and power-up procedures under the design owner’s control; do not borrow them from an unrelated example chip.

Start by proving the test setup can observe the intended behavior. A chip that appears inactive may have a board, socket, pin-map, clock, reset or configuration problem. Preserve those setup facts before attributing a failure to silicon.

Keep package orientation and device identity visible from the assembly record to the bench log. Where wafer coordinates and probe results are supplied, retain their relationship to the packaged sample so unexpected results can be investigated.

Step 5: check the schedule and deliverables

• Who supplies the probe card, socket, evaluation board and test program?
• Which tasks can begin before fabrication finishes?
• Who reviews and accepts the bond diagram and pin map?
• What reports accompany the samples, and in which format?
• Who handles shipment, destination documentation and sample receipt?

The output is a package/test plan with named owners and open decisions. Add it to the MPW brief early, even if some choices remain provisional. Cost and delivery dates require the actual scope to be confirmed.

Continue the MPW tutorial

Use the GDS handoff tutorial to connect the pad-map revision to final design data. Follow the tapeout-to-first-silicon checklist for the full sequence, or return to MPW fundamentals.

For a project review, see MST’s MPW coordination scope and share only non-confidential requirements at public intake.

Technical review: 16 September 2026. The numeric allocation is a teaching example. Package compatibility, test limits, sample yield and delivery must be established for the actual design.