I have a chip design. How do I get working first silicon?
Start by defining process fit, design readiness, the controlled PDK and data path, prototype quantity, package and test scope, then select a partner-confirmed run.
Semiconductor · MPW
HHGrace mature-node MPW screening starts with a brief
Start a 2026 HHGrace mature-node MPW schedule enquiry with non-confidential assumptions. MST helps overseas fabless companies, universities, research teams and industrial chip developers prepare a reviewable brief for process/node fit, NDA/PDK path, package/test scope, schedule target and formal quotation workflow. Schedule window, availability and quotation are confirmed case by case after requirement review.
2026 MPW schedule screening
HHGrace mature-node MPW platform intake table
This is the public schedule-screening entry for 2026 HHGrace mature-node MPW RFQs through MST Singapore. It is intentionally not a public price list or guaranteed shuttle calendar: exact run window, registration deadline, GDS/data-in deadline, PDK/NDA path, availability and quotation are confirmed case by case after requirement review.
Public 2026 platform and schedule-screening view
Use this table the same way a buyer would use a public MPW schedule page: identify the likely platform, then submit a non-confidential first brief so MST can check the current schedule window and quote path.
| Node | Platform | Fit | 2026 status | What to send first | Next step |
|---|---|---|---|---|---|
| 90nm | Low-power BCD | BCD and power-management prototype requirements where voltage class, die area, package/test and samples need review. | 2026 RFQ screening open | Node target, voltage class, die estimate, sample count, package/test assumptions and target quarter. | Start fit screening → |
| 90nm | Embedded eFlash | Embedded non-volatile memory and mixed-signal prototype RFQs that can start from a non-confidential brief. | 2026 RFQ screening open | Memory/process need, die estimate, package/test assumptions, PDK/NDA status and target quarter. | Start fit screening → |
| 55nm | SiGe BiCMOS | RF, high-speed and mixed-signal prototype screening where process fit and package/test scope must be checked first. | 2026 RFQ screening open | RF/high-speed requirement, rough die size, frequency/use context, package/test assumptions and schedule target. | Start fit screening → |
| 55nm | Low-power BCD | Low-power BCD and power-management inquiries that need node, voltage, die-area, schedule and end-use review. | 2026 RFQ screening open | Voltage class, application context, die estimate, target samples and package/test assumptions. | Start fit screening → |
| 55nm | Logic / eFlash | Logic or embedded-Flash prototype needs where MST can prepare a reviewable RFQ before design-IP exchange. | 2026 RFQ screening open | Logic/eFlash need, die estimate, package/test assumptions, PDK/NDA status and preferred tapeout window. | Start fit screening → |
| 40nm | Logic / eFlash | 40nm logic, low-power or embedded-Flash prototype routes. Partner acceptance and schedule fit are required. | 2026 RFQ screening open | Node/process need, die estimate, package/test assumptions, target quarter, country and end-use context. | Start fit screening → |
Internal shuttle codes, supplier emails, booking deadlines, GDS/data-in deadlines and supplier cost are not published. MST confirms them only through the formal review and quotation path.
Start a non-confidential MPW enquiry →
One brief · three clear owners
Know what happens before you start the enquiry.
The first screen is intentionally non-confidential. It prepares a reviewable request; it does not reserve capacity, promise a slot or replace fab confirmation.
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01 · You send
A non-confidential first brief
Target node or process family, rough die area, sample need, package/test assumptions, target quarter, country and end-use context. No GDS or protected design IP.
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02 · MST reviews and returns
A gap list and review route
MST checks process fit, missing inputs, NDA/PDK path, package/probe/test scope and whether the request is ready for partner review.
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03 · Fab confirms
Availability, schedule and quotation
The qualified route, process eligibility, capacity, slot, deadline, PDK access, price and order acceptance remain fab-confirmed case by case.
Choose the right first step
Start before you share design files
Most early MPW visitors are not ready to send a full tapeout package. MST gives four lower-risk paths: compare access routes, check readiness, build a no-GDS first brief, or start a non-confidential enquiry for manual review.
Step 00 · Access route
Compare which MPW path can review the case
Use the access map when the first question is not design readiness, but which route, region, eligibility gate, NDA/PDK path and review owner can handle the request.
Open access map →Step 01 · Self-check
Check whether the request is reviewable
Use the readiness checker when you know the target application, approximate node or process family, rough die size, samples, package/test assumptions or schedule pressure.
Open readiness checker →Step 02 · Build brief
Generate a no-GDS RFQ brief
Use the RFQ pack builder to turn node, process family, die area, sample target, package/test assumptions, timeline and end-use context into a non-confidential first-screening brief.
Build RFQ brief → Download template ↓Step 03 · Manual review
Submit the brief for MST screening
Send the non-confidential brief when you want MST to screen process fit, package/test scope, NDA/PDK route, eligibility context and partner-review readiness.
Start a non-confidential MPW enquiry →
MPW readiness review
Start with a no-GDS MPW brief.
Send node range, process family, rough die area, sample target, package/test assumptions, timeline and end-use context. MST screens readiness before sensitive design data moves.
Coverage
Indicative process window. Final node and process are confirmed case by case with a qualified partner.
MPW-COVERAGE · indicative
partner-confirmed
Nodes0.35um-40nm across mature-node and specialty processes.
Advanced edge28 / 22nm - case by case, subject to partner confirmation.
ProcessesAnalog / Mixed-signal · BCD / Power · eNVM / eFlash · RF · High-voltage.
Run typeShared-reticle multi-project wafer coordination and tapeout routing.
At intakeHigh-level requirements only - no GDS / netlist / RTL before NDA.
Useful tools for MPW planning
Use these tools before submitting an RFQ: plan shared-reticle floorplans, estimate gross/good dies, inspect local GDS metadata, compare cost share, and turn high-level parameters into an RFQ link. Everything runs in your browser; the GDS tool does not upload files, and RFQ intake still uses non-confidential summaries only.
See all tools →Tool 00 · Fit-check
3-step MPW fit-check
Answer high-level process, prototype-scope and compliance-boundary questions, then open the MPW RFQ form with non-confidential answers pre-filled.
Open readiness check →Tool 01 · Reticle planning
MPW Reticle & Wafer Planner
Pack several projects into one shared reticle, step it across the wafer, estimate gross/good dies and each project area-based cost share.
Open planner →Tool 02 · Fast estimate
MPW Prototype Cost Estimator
Estimate gross dies per wafer, shared-reticle utilization, indicative mature-node cost range, shuttle timing and tapeout readiness.
Open estimator →Tool 03 · Local GDS check
Local GDSII Inspector
Inspect a .gds file fully in your browser: top cell, die size, layers, cell tree and element counts. Nothing is uploaded - use the metadata to build a non-confidential RFQ summary.
Open GDS inspector →Reference · Access map
Non-Western MPW Access Map
A neutral, sourced comparison of MPW routes - MOSIS, Europractice, Muse, IMEC and others - focused on the question others omit: which route a non-US / non-EU team can actually use. Eligibility, pricing model and access gates, every figure dated to its source.
Open access map →
Example RFQ packets
What a reviewable MPW packet looks like
These are illustrative, non-confidential examples. They show the level of scope MST needs for first screening and what remains for NDA-controlled review.
Example 01
180nm mixed-signal sensor ASIC
Customer provides: Customer provides target node range, analog/mixed-signal function, rough die area, sample count, package preference, measurement goal and end-use context.
MST returns: MST returns missing questions, possible process-family fit, package/probe/test checklist, NDA/PDK route notes and partner-review readiness.
Later controlled path: GDS, schematics, netlist, PDK files and detailed circuit implementation stay out of the public intake and move only after the controlled path is clear.
Example 02
350nm high-voltage / BCD prototype
Customer provides: Customer provides voltage class, device-option assumptions, pad/package direction, die-size range, safety or industrial-control use case, target samples and timeline.
MST returns: MST flags process-fit uncertainty, required partner questions, packaging and reliability assumptions, compliance context and quote-readiness gaps.
Later controlled path: Exact device stack, proprietary circuit detail, layout files and partner-specific design rules wait for NDA/PDK and qualified technical review.
Example 03
65/55nm RF or eNVM feasibility inquiry
Customer provides: Customer provides RF band or memory need at a non-confidential level, acceptable node range, rough die area, package/test assumptions and schedule pressure.
MST returns: MST separates public planning questions from NDA-gated questions and prepares a partner-review packet focused on feasibility, access path and missing assumptions.
Later controlled path: Model files, IP blocks, proprietary layout, performance-sensitive schematics and process-specific data belong in the later controlled exchange.
Start with your problem—not an industry acronym
Twenty high-intent routes to first silicon
You may call it prototype tapeout, a shuttle run, a small engineering batch, packaged samples or simply “how do I get this chip made?” Choose the problem closest to yours; each route ends in an evidence checklist and a human-reviewed next step.
From design idea to first silicon 4 routes
I only have RTL, schematics or a preliminary layout. What comes next?
A non-confidential readiness review can identify missing architecture, implementation, verification, signoff and commercial inputs before any protected design files move.
Can I assess the route or request a quote before final GDS?
Yes. A first review can use node, process, die-area, sample, package, test and timing assumptions; price, slot and data acceptance still require formal confirmation.
What if a foundry will not respond to my startup or small team?
Use a qualified access and coordination route that can screen the entity, end use, process need, NDA and PDK path before presenting a reviewable request.
Process and foundry-route fit 4 routes
How do I choose among 90nm BCD, 55nm eFlash and 40nm low-power logic?
Choose by voltage, embedded-memory, analog and RF needs, qualified IP, IO, die area, package, test and accessible ecosystem—not nominal node alone.
Should a power-management MCU use BCD, eFlash or a logic process?
Map voltage devices, non-volatile memory, digital density, analog precision, IO and reliability needs first; a partner must then confirm the available process options.
How can a qualified project enter the HHGrace NDA, PDK and technical-review path?
Begin with a non-confidential requirement brief and entity and end-use context. NDA, PDK eligibility, technical fit and access are confirmed through the controlled partner path.
How can an overseas or Korean fabless team access an Asian mature-node MPW route?
Country, customer type, end use, process family, schedule and data controls determine the realistic route; MST Singapore can structure the first review without public IP exchange.
Urgent schedule and Fast-Track screening 4 routes
How do I find and qualify for the next suitable shuttle run?
Compare process fit, registration and data-in gates, minimum area, deliverables and readiness, then request the latest partner-confirmed window instead of relying on a static calendar.
What is the fastest realistic route to first silicon?
The fastest route starts with a complete brief and a design close to the relevant signoff gate. Priority triage can reduce avoidable waiting, but no elapsed time is guaranteed.
I urgently need 20–100 packaged prototypes. Which path should I use?
Define whether you need wafers, loose die or packaged and tested units, then coordinate wafer run, probe, dicing, assembly, final test and logistics as separate confirmed scopes.
What can I do if I missed a shuttle deadline or the preferred run is unavailable?
Recheck nearby nodes and process options, another operator or run, design readiness and whether an engineering or dedicated route better fits the business deadline.
Cost, readiness and quotation 4 routes
What does an MPW or engineering prototype run cost?
Cost depends on process option, minimum area, die size, wafer allocation, masks, package, probe, final test, logistics and schedule; a public node name is not a quote.
How do die area, sample count, package and test change the quotation?
Die area can affect shared-wafer allocation while deliverable quantity, yield assumptions, package choice, probe and final-test coverage change downstream scope and cost.
My design passes DRC and LVS. What still remains before first silicon?
Foundry-specific signoff, final data acceptance, run registration, mask and wafer execution, probe, dicing, packaging, final test, logistics and bring-up can still remain.
What should I include in the first non-confidential MPW brief?
Include country and end use, target node or range, process family, die estimate, samples, package and test assumptions, timing and NDA or PDK status—without design IP.
Packaging, test and the route after MPW 4 routes
Who handles wafer probe, dicing, package assembly and sample delivery?
The foundry, probe house, OSAT, test house, logistics provider and customer may own different steps. The quotation must name the deliverable and each confirmed owner.
Who coordinates wafer probe, final test, characterization and reliability work?
Start with the intended evidence and sample form. Test coverage, fixtures, ATE programs, characterization and reliability plans are separate scopes that need named ownership.
How should I plan for ECO or re-spin after first-silicon bring-up?
Define bring-up evidence, failure isolation, change scope, reusable masks or layers if applicable, verification closure and the decision gate between another MPW and a dedicated run.
How do I move from MPW to an engineering lot, qualification and volume production?
Use first-silicon evidence to decide on ECO, another prototype or a dedicated engineering route, then define qualification, test, supply, quality and commercial gates.
Public first contact is non-confidential. Do not send GDS, OASIS, RTL, netlists, schematics, PDK files or proprietary IP until the controlled NDA/data path is confirmed.
Frequently asked
The questions engineers and procurement teams ask before submitting a brief.
Can I submit an MPW RFQ without uploading GDS?
Yes. Intake is high-level requirements only: node, process family, die area, volume and timeline. Design detail is only exchanged later, under NDA.
What happens after I submit?
A manual compliance review runs first. Then we screen process-fit, set up the PDK/NDA path, and coordinate the partner-confirmed next step. Pricing, schedule and availability are confirmed case by case.
What usually drives MPW cost and schedule?
The main drivers are node, process option, shuttle timing, die area, mask/reticle share, wafer allocation, packaging, wafer probe, final test, logistics and the amount of partner review required before the case is ready.
Which nodes and processes are covered?
Nodes from 0.35um to 40nm across mature-node and specialty processes, with 28/22nm considered case by case. Final fit is partner-confirmed.
Is mature-node MPW export-controlled?
Every RFQ passes customer, country and end-use screening. Sensitive cases go to manual review and may be held.
Start with a high-level brief
Ready to scope your run?
Send node, process family, die area, sample quantity and timeline - no design IP. MST prepares the request for review and moves sensitive files only through the proper NDA-controlled path.