I have a chip design. How do I get working first silicon?
Start by defining process fit, design readiness, the controlled PDK and data path, prototype quantity, package and test scope, then select a partner-confirmed run.
半導体 · HHGrace MPW
HHGrace MPW 代理・キャパシティ照会窓口
MST Singaporeは、海外向けキャパシティ照会、顧客受付、プロジェクト調整を担う非独占HHGrace MPW代理です。非機密のnode、process、die、package/test、希望時期をfab審査用briefにまとめます。実際のキャパシティ、slot、日程、PDK、見積、受入は案件ごとに確認されます。
2026 MPW schedule screening
HHGrace mature-node MPW platform intake table
This is the public schedule-screening entry for 2026 HHGrace mature-node MPW RFQs through MST Singapore. It is intentionally not a public price list or guaranteed shuttle calendar: exact run window, registration deadline, GDS/data-in deadline, PDK/NDA path, availability and quotation are confirmed case by case after requirement review.
Public 2026 platform and schedule-screening view
Use this table the same way a buyer would use a public MPW schedule page: identify the likely platform, then submit a non-confidential first brief so MST can check the current schedule window and quote path.
| Node | Platform | Fit | 2026 status | What to send first | 次のステップ |
|---|---|---|---|---|---|
| 90nm | Low-power BCD | BCD and power-management prototype requirements where voltage class, die area, package/test and samples need review. | 2026 RFQ screening open | Node target, voltage class, die estimate, sample count, package/test assumptions and target quarter. | 適合性チェックを始める → |
| 90nm | Embedded eFlash | Embedded non-volatile memory and mixed-signal prototype RFQs that can start from a non-confidential brief. | 2026 RFQ screening open | Memory/process need, die estimate, package/test assumptions, PDK/NDA status and target quarter. | 適合性チェックを始める → |
| 55nm | SiGe BiCMOS | RF, high-speed and mixed-signal prototype screening where process fit and package/test scope must be checked first. | 2026 RFQ screening open | RF/high-speed requirement, rough die size, frequency/use context, package/test assumptions and schedule target. | 適合性チェックを始める → |
| 55nm | Low-power BCD | Low-power BCD and power-management inquiries that need node, voltage, die-area, schedule and end-use review. | 2026 RFQ screening open | Voltage class, application context, die estimate, target samples and package/test assumptions. | 適合性チェックを始める → |
| 55nm | Logic / eFlash | Logic or embedded-Flash prototype needs where MST can prepare a reviewable RFQ before design-IP exchange. | 2026 RFQ screening open | Logic/eFlash need, die estimate, package/test assumptions, PDK/NDA status and preferred tapeout window. | 適合性チェックを始める → |
| 40nm | Logic / eFlash | 40nm logic, low-power or embedded-Flash prototype routes. Partner acceptance and schedule fit are required. | 2026 RFQ screening open | Node/process need, die estimate, package/test assumptions, target quarter, country and end-use context. | 適合性チェックを始める → |
Internal shuttle codes, supplier emails, booking deadlines, GDS/data-in deadlines and supplier cost are not published. MST confirms them only through the formal review and quotation path.
非機密の MPW 問い合わせを始める →
1つのbrief · 3者の明確な責任
問い合わせ前に、その後の流れを確認してください。
初回確認では非機密情報のみを使い、レビュー可能な依頼を準備します。キャパシティやslotを確保・保証するものではなく、fabの確認に代わるものでもありません。
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01 · お客様が送る情報
非機密の初回brief
対象ノードまたはプロセス、概算die面積、サンプル、package/testの前提、希望四半期、国、最終用途。GDSや保護対象の設計IPは送らないでください。
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02 · MSTが確認して返す内容
不足項目とレビュー経路
MSTはプロセス適合性、不足情報、NDA/PDK経路、package・wafer probe・testの範囲、パートナーレビューへの準備状況を確認します。
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03 · Fabが確認
可用性、日程、見積
適用経路、プロセス適格性、キャパシティ、slot、締切、PDKアクセス、価格、受入可否は、fabが案件ごとに確認します。
最初のステップを選択
設計ファイルを共有する前に始める
多くの初期MPW訪問者は、完全なtapeout packageを送れる段階ではありません。MSTは、アクセスルート比較、準備度確認、no-GDS brief作成、非機密RFQの手動レビューという4つの低リスク入口を提供します。
Step 00 · アクセスルート
どのMPWルートが案件をレビューできるか比較する
最初の問題が設計準備度ではなく、どのルート、地域、適格性ゲート、NDA/PDKパス、レビューownerが依頼を扱えるかである場合、アクセスマップを使います。
access map を開く →Step 01 · セルフチェック
依頼がレビュー可能か確認する
対象アプリケーション、おおよその node または process family、die size、sample 数、package/test assumptions、schedule pressure が分かる場合は readiness checker を使えます。
Readiness checker を開く →Step 02 · brief 作成
GDS なしの RFQ brief を作成
RFQ pack builder で、node、process family、die area、sample target、package/test assumptions、timeline、end-use context を非機密の first-screening brief に整理します。
RFQ brief を作成 → テンプレートをダウンロード ↓Step 03 · 手動レビュー
brief を MST screening に提出
process fit、package/test scope、NDA/PDK route、eligibility context、partner-review readiness の確認が必要な場合、非機密 brief を送信してください。
非機密の MPW 問い合わせを始める →
MPW readiness review
GDS なしの MPW brief から開始してください。
node range、process family、rough die area、sample target、package/test assumptions、timeline、end-use context を送ってください。MST は機密設計データを移動する前に readiness を確認します。
対応範囲
目安となるプロセス範囲です。最終ノードとプロセスは適格パートナーが案件ごとに確認します。
MPW 対応範囲 · 目安
パートナー確認済み
ノード0.35um-40nm 成熟ノードおよび特殊プロセスに対応。
先端寄りノード28 / 22nm - パートナー確認を前提に案件ごとに検討。
プロセスアナログ / ミックスドシグナル · BCD / パワー · eNVM / eFlash · RF · 高電圧。
run 種別共有 reticle の multi-project wafer 調整と tapeout ルーティング。
intake 時点高レベル要件のみ。NDA 前は GDS / netlist / RTL 不要。
MPW 計画に使えるツール
RFQ 送信前に、共有 reticle 計画、gross/good die 推定、ローカル GDS メタデータ確認、コスト分担比較、高レベルパラメータから RFQ リンク生成ができます。すべてブラウザ内で動作し、GDS ツールはファイルをアップロードしません。RFQ intake も非機密サマリのみです。
すべてのツールを見る →ツール 00 · 適合チェック
3 ステップ MPW 適合チェック
プロセス、プロトタイプ範囲、コンプライアンス境界に関する高レベル質問に答え、非機密回答を入力済みの MPW RFQ フォームを開きます。
準備度チェックを開く →Tool 01 · Reticle planning
MPW Reticle & Wafer Planner
Pack several projects into one shared reticle, step it across the wafer, estimate gross/good dies and each project area-based cost share.
Open planner →Tool 02 · Fast estimate
MPW プロトタイプ費用推定
Estimate gross dies per wafer, shared-reticle utilization, indicative mature-node cost range, shuttle timing and tapeout readiness.
Open estimator →Tool 03 · Local GDS check
ローカル GDSII Inspector
Inspect a .gds file fully in your browser: top cell, die size, layers, cell tree and element counts. Nothing is uploaded - use the metadata to build a non-confidential RFQ summary.
Open GDS inspector →Reference · Access map
非欧米チーム向け MPW Access Map
MOSIS、Europractice、Muse、IMEC などの MPW ルートを、出典付きで中立的に比較します。米国/EU 以外のチームが実際に利用できる経路に焦点を当てます。
access map を開く →
Example RFQ packets
What a reviewable MPW packet looks like
These are illustrative, non-confidential examples. They show the level of scope MST needs for first screening and what remains for NDA-controlled review.
Example 01
180nm mixed-signal sensor ASIC
Customer provides: Customer provides target node range, analog/mixed-signal function, rough die area, sample count, package preference, measurement goal and end-use context.
MST returns: MST returns missing questions, possible process-family fit, package/probe/test checklist, NDA/PDK route notes and partner-review readiness.
Later controlled path: GDS, schematics, netlist, PDK files and detailed circuit implementation stay out of the public intake and move only after the controlled path is clear.
Example 02
350nm high-voltage / BCD prototype
Customer provides: Customer provides voltage class, device-option assumptions, pad/package direction, die-size range, safety or industrial-control use case, target samples and timeline.
MST returns: MST flags process-fit uncertainty, required partner questions, packaging and reliability assumptions, compliance context and quote-readiness gaps.
Later controlled path: Exact device stack, proprietary circuit detail, layout files and partner-specific design rules wait for NDA/PDK and qualified technical review.
Example 03
65/55nm RF or eNVM feasibility inquiry
Customer provides: Customer provides RF band or memory need at a non-confidential level, acceptable node range, rough die area, package/test assumptions and schedule pressure.
MST returns: MST separates public planning questions from NDA-gated questions and prepares a partner-review packet focused on feasibility, access path and missing assumptions.
Later controlled path: Model files, IP blocks, proprietary layout, performance-sensitive schematics and process-specific data belong in the later controlled exchange.
Start with your problem—not an industry acronym
Twenty high-intent routes to first silicon
You may call it prototype tapeout, a shuttle run, a small engineering batch, packaged samples or simply “how do I get this chip made?” Choose the problem closest to yours; each route ends in an evidence checklist and a human-reviewed next step.
From design idea to first silicon 4 routes
I only have RTL, schematics or a preliminary layout. What comes next?
A non-confidential readiness review can identify missing architecture, implementation, verification, signoff and commercial inputs before any protected design files move.
Can I assess the route or request a quote before final GDS?
Yes. A first review can use node, process, die-area, sample, package, test and timing assumptions; price, slot and data acceptance still require formal confirmation.
What if a foundry will not respond to my startup or small team?
Use a qualified access and coordination route that can screen the entity, end use, process need, NDA and PDK path before presenting a reviewable request.
Process and foundry-route fit 4 routes
How do I choose among 90nm BCD, 55nm eFlash and 40nm low-power logic?
Choose by voltage, embedded-memory, analog and RF needs, qualified IP, IO, die area, package, test and accessible ecosystem—not nominal node alone.
Should a power-management MCU use BCD, eFlash or a logic process?
Map voltage devices, non-volatile memory, digital density, analog precision, IO and reliability needs first; a partner must then confirm the available process options.
How can a qualified project enter the HHGrace NDA, PDK and technical-review path?
Begin with a non-confidential requirement brief and entity and end-use context. NDA, PDK eligibility, technical fit and access are confirmed through the controlled partner path.
How can an overseas or Korean fabless team access an Asian mature-node MPW route?
Country, customer type, end use, process family, schedule and data controls determine the realistic route; MST Singapore can structure the first review without public IP exchange.
Urgent schedule and Fast-Track screening 4 routes
How do I find and qualify for the next suitable shuttle run?
Compare process fit, registration and data-in gates, minimum area, deliverables and readiness, then request the latest partner-confirmed window instead of relying on a static calendar.
What is the fastest realistic route to first silicon?
The fastest route starts with a complete brief and a design close to the relevant signoff gate. Priority triage can reduce avoidable waiting, but no elapsed time is guaranteed.
I urgently need 20–100 packaged prototypes. Which path should I use?
Define whether you need wafers, loose die or packaged and tested units, then coordinate wafer run, probe, dicing, assembly, final test and logistics as separate confirmed scopes.
What can I do if I missed a shuttle deadline or the preferred run is unavailable?
Recheck nearby nodes and process options, another operator or run, design readiness and whether an engineering or dedicated route better fits the business deadline.
Cost, readiness and quotation 4 routes
What does an MPW or engineering prototype run cost?
Cost depends on process option, minimum area, die size, wafer allocation, masks, package, probe, final test, logistics and schedule; a public node name is not a quote.
How do die area, sample count, package and test change the quotation?
Die area can affect shared-wafer allocation while deliverable quantity, yield assumptions, package choice, probe and final-test coverage change downstream scope and cost.
My design passes DRC and LVS. What still remains before first silicon?
Foundry-specific signoff, final data acceptance, run registration, mask and wafer execution, probe, dicing, packaging, final test, logistics and bring-up can still remain.
What should I include in the first non-confidential MPW brief?
Include country and end use, target node or range, process family, die estimate, samples, package and test assumptions, timing and NDA or PDK status—without design IP.
Packaging, test and the route after MPW 4 routes
Who handles wafer probe, dicing, package assembly and sample delivery?
The foundry, probe house, OSAT, test house, logistics provider and customer may own different steps. The quotation must name the deliverable and each confirmed owner.
Who coordinates wafer probe, final test, characterization and reliability work?
Start with the intended evidence and sample form. Test coverage, fixtures, ATE programs, characterization and reliability plans are separate scopes that need named ownership.
How should I plan for ECO or re-spin after first-silicon bring-up?
Define bring-up evidence, failure isolation, change scope, reusable masks or layers if applicable, verification closure and the decision gate between another MPW and a dedicated run.
How do I move from MPW to an engineering lot, qualification and volume production?
Use first-silicon evidence to decide on ECO, another prototype or a dedicated engineering route, then define qualification, test, supply, quality and commercial gates.
Public first contact is non-confidential. Do not send GDS, OASIS, RTL, netlists, schematics, PDK files or proprietary IP until the controlled NDA/data path is confirmed.
よくある質問
brief 送信前にエンジニアや procurement チームがよく聞く質問です。
GDS をアップロードせずに MPW RFQ を送れますか？
はい。intake はノード、プロセスファミリ、die 面積、数量、時期などの高レベル要件のみです。設計詳細は後で NDA 下で交換します。
送信後は何が起きますか？
まず手動コンプライアンスレビューを行います。その後、プロセス適合を確認し、PDK/NDA 経路を設定し、パートナー確認後の次ステップを調整します。価格、日程、可用性はケースごとに確認されます。
MPW のコストと日程は通常何で決まりますか？
主な要因は、ノード、プロセスオプション、shuttle タイミング、die 面積、mask/reticle 分担、wafer allocation、パッケージ、wafer probe、final test、物流、そして案件がレビュー可能になるまでに必要なパートナー確認の範囲です。
どのノードとプロセスに対応しますか？
0.35um から 40nm の成熟ノードと特殊プロセスに対応し、28/22nm は案件ごとに検討します。最終適合はパートナー確認です。
成熟ノード MPW は輸出管理対象ですか？
すべての RFQ は顧客、国、最終用途のスクリーニングを受けます。センシティブな案件は手動レビューに入り、保留される場合があります。
高レベル brief から開始
MPWから初回シリコンまでの経路を計画しますか？
ノード／プロセス適合、希望日程、初回シリコン評価、パッケージ／テスト、サンプルハンドリング、リスピン要件を非機密の概要から共有してください。MSTがレビュー経路へ振り分け、実現可能性、可用性、日程、見積もりは案件ごとに確認します。