I have a chip design. How do I get working first silicon?
Start by defining process fit, design readiness, the controlled PDK and data path, prototype quantity, package and test scope, then select a partner-confirmed run.
MST Singapore actúa como agente no exclusivo de HHGrace para consultas de capacidad MPW, admisión de clientes y coordinación internacional. Convertimos un brief no confidencial de nodo, proceso, die, package/test y fecha en una solicitud revisable por la fab. Capacidad, slot, calendario, PDK, cotización y aceptación se confirman caso por caso.
This is the public schedule-screening entry for 2026 HHGrace mature-node MPW RFQs through MST Singapore. It is intentionally not a public price list or guaranteed shuttle calendar: exact run window, registration deadline, GDS/data-in deadline, PDK/NDA path, availability and quotation are confirmed case by case after requirement review.
Use this table the same way a buyer would use a public MPW schedule page: identify the likely platform, then submit a non-confidential first brief so MST can check the current schedule window and quote path.
| Node | Platform | Fit | 2026 status | What to send first | Siguiente paso |
|---|---|---|---|---|---|
| 90nm | Low-power BCD | BCD and power-management prototype requirements where voltage class, die area, package/test and samples need review. | 2026 RFQ screening open | Node target, voltage class, die estimate, sample count, package/test assumptions and target quarter. | Iniciar evaluación de encaje → |
| 90nm | Embedded eFlash | Embedded non-volatile memory and mixed-signal prototype RFQs that can start from a non-confidential brief. | 2026 RFQ screening open | Memory/process need, die estimate, package/test assumptions, PDK/NDA status and target quarter. | Iniciar evaluación de encaje → |
| 55nm | SiGe BiCMOS | RF, high-speed and mixed-signal prototype screening where process fit and package/test scope must be checked first. | 2026 RFQ screening open | RF/high-speed requirement, rough die size, frequency/use context, package/test assumptions and schedule target. | Iniciar evaluación de encaje → |
| 55nm | Low-power BCD | Low-power BCD and power-management inquiries that need node, voltage, die-area, schedule and end-use review. | 2026 RFQ screening open | Voltage class, application context, die estimate, target samples and package/test assumptions. | Iniciar evaluación de encaje → |
| 55nm | Logic / eFlash | Logic or embedded-Flash prototype needs where MST can prepare a reviewable RFQ before design-IP exchange. | 2026 RFQ screening open | Logic/eFlash need, die estimate, package/test assumptions, PDK/NDA status and preferred tapeout window. | Iniciar evaluación de encaje → |
| 40nm | Logic / eFlash | 40nm logic, low-power or embedded-Flash prototype routes. Partner acceptance and schedule fit are required. | 2026 RFQ screening open | Node/process need, die estimate, package/test assumptions, target quarter, country and end-use context. | Iniciar evaluación de encaje → |
La primera evaluación usa solo información no confidencial y prepara una solicitud revisable; no reserva capacidad, promete un slot ni sustituye la confirmación de la fab.
Nodo o proceso objetivo, área aproximada del die, muestras, supuestos de encapsulado/prueba, trimestre objetivo, país y uso final. Sin GDS ni IP de diseño protegida.
MST revisa el encaje del proceso, datos faltantes, ruta NDA/PDK, alcance de encapsulado, prueba de oblea y prueba final, y la preparación para revisión del socio.
Ruta, elegibilidad de proceso, capacidad, slot, fecha límite, acceso PDK, precio y aceptación se confirman con la fab caso por caso.
La mayoría de visitantes MPW tempranos no están listos para enviar un paquete completo de tapeout. MST ofrece cuatro rutas de menor riesgo: comparar rutas de acceso, revisar preparación, crear un brief no-GDS o enviar una RFQ no confidencial para revisión manual.
Use el mapa de acceso cuando la primera pregunta no sea la preparación del diseño, sino qué ruta, región, puerta de elegibilidad, NDA/PDK y owner de revisión pueden manejar la solicitud.
Abrir mapa de acceso →Use el readiness checker cuando conozca la aplicación objetivo, el nodo o familia de proceso aproximados, tamaño de die, muestras, supuestos de package/test o presión de calendario.
Abrir readiness checker →Use el RFQ pack builder para convertir nodo, familia de proceso, área de die, muestras, package/test, calendario y end-use en un brief no confidencial de primera revisión.
Crear brief RFQ → Descargar plantilla ↓Envíe el brief no confidencial cuando quiera que MST revise process fit, alcance package/test, ruta NDA/PDK, contexto de elegibilidad y preparación para revisión de partner.
Iniciar una consulta MPW no confidencial →Envíe rango de nodo, familia de proceso, área aproximada de die, objetivo de muestras, supuestos package/test, calendario y contexto de uso final. MST revisa la preparación antes de mover datos sensibles de diseño.
Ventana indicativa de proceso. El nodo y proceso final se confirman caso por caso con un socio cualificado.
Usa estas herramientas antes de enviar un RFQ: planifica retículas compartidas, estima dies brutos/buenos, inspecciona metadatos GDS localmente, compara reparto de coste y convierte parámetros de alto nivel en un enlace RFQ. Todo corre en tu navegador; la herramienta GDS no sube archivos y la entrada RFQ sigue usando solo resúmenes no confidenciales.
Ver todas las herramientas →Responde preguntas de alto nivel sobre proceso, alcance de prototipo y límite de cumplimiento; después abre el RFQ de MPW con respuestas no confidenciales prellenadas.
Abrir comprobación →Empaque varios proyectos en una retícula compartida, simule el stepping sobre el wafer, estime gross/good dies y reparto de coste por área.
Abrir planificador →Estime gross dies por wafer, uso de retícula compartida, rango indicativo mature-node, tiempo de shuttle y readiness de tapeout.
Abrir estimador →Inspeccione un .gds en el navegador: top cell, tamaño de die, capas, cell tree y conteos. Nada se sube; use metadata para un resumen RFQ no confidencial.
Abrir inspector GDS →Comparación neutral y con fuentes de rutas MPW como MOSIS, Europractice, Muse, IMEC y otras, centrada en una pregunta práctica: qué ruta puede usar realmente un equipo fuera de EE. UU. o la UE.
Abrir mapa de acceso →Ejemplos ilustrativos y no confidenciales: muestran el nivel de alcance para screening inicial y lo que queda para revisión bajo NDA.
El cliente aporta: Customer provides target node range, analog/mixed-signal function, rough die area, sample count, package preference, measurement goal and end-use context.
MST devuelve: MST returns missing questions, possible process-family fit, package/probe/test checklist, NDA/PDK route notes and partner-review readiness.
Ruta controlada posterior: GDS, schematics, netlist, PDK files and detailed circuit implementation stay out of the public intake and move only after the controlled path is clear.
El cliente aporta: Customer provides voltage class, device-option assumptions, pad/package direction, die-size range, safety or industrial-control use case, target samples and timeline.
MST devuelve: MST flags process-fit uncertainty, required partner questions, packaging and reliability assumptions, compliance context and quote-readiness gaps.
Ruta controlada posterior: Exact device stack, proprietary circuit detail, layout files and partner-specific design rules wait for NDA/PDK and qualified technical review.
El cliente aporta: Customer provides RF band or memory need at a non-confidential level, acceptable node range, rough die area, package/test assumptions and schedule pressure.
MST devuelve: MST separates public planning questions from NDA-gated questions and prepares a partner-review packet focused on feasibility, access path and missing assumptions.
Ruta controlada posterior: Model files, IP blocks, proprietary layout, performance-sensitive schematics and process-specific data belong in the later controlled exchange.
You may call it prototype tapeout, a shuttle run, a small engineering batch, packaged samples or simply “how do I get this chip made?” Choose the problem closest to yours; each route ends in an evidence checklist and a human-reviewed next step.
Start by defining process fit, design readiness, the controlled PDK and data path, prototype quantity, package and test scope, then select a partner-confirmed run.
A non-confidential readiness review can identify missing architecture, implementation, verification, signoff and commercial inputs before any protected design files move.
Yes. A first review can use node, process, die-area, sample, package, test and timing assumptions; price, slot and data acceptance still require formal confirmation.
Use a qualified access and coordination route that can screen the entity, end use, process need, NDA and PDK path before presenting a reviewable request.
Choose by voltage, embedded-memory, analog and RF needs, qualified IP, IO, die area, package, test and accessible ecosystem—not nominal node alone.
Map voltage devices, non-volatile memory, digital density, analog precision, IO and reliability needs first; a partner must then confirm the available process options.
Begin with a non-confidential requirement brief and entity and end-use context. NDA, PDK eligibility, technical fit and access are confirmed through the controlled partner path.
Country, customer type, end use, process family, schedule and data controls determine the realistic route; MST Singapore can structure the first review without public IP exchange.
Compare process fit, registration and data-in gates, minimum area, deliverables and readiness, then request the latest partner-confirmed window instead of relying on a static calendar.
The fastest route starts with a complete brief and a design close to the relevant signoff gate. Priority triage can reduce avoidable waiting, but no elapsed time is guaranteed.
Define whether you need wafers, loose die or packaged and tested units, then coordinate wafer run, probe, dicing, assembly, final test and logistics as separate confirmed scopes.
Recheck nearby nodes and process options, another operator or run, design readiness and whether an engineering or dedicated route better fits the business deadline.
Cost depends on process option, minimum area, die size, wafer allocation, masks, package, probe, final test, logistics and schedule; a public node name is not a quote.
Die area can affect shared-wafer allocation while deliverable quantity, yield assumptions, package choice, probe and final-test coverage change downstream scope and cost.
Foundry-specific signoff, final data acceptance, run registration, mask and wafer execution, probe, dicing, packaging, final test, logistics and bring-up can still remain.
Include country and end use, target node or range, process family, die estimate, samples, package and test assumptions, timing and NDA or PDK status—without design IP.
The foundry, probe house, OSAT, test house, logistics provider and customer may own different steps. The quotation must name the deliverable and each confirmed owner.
Start with the intended evidence and sample form. Test coverage, fixtures, ATE programs, characterization and reliability plans are separate scopes that need named ownership.
Define bring-up evidence, failure isolation, change scope, reusable masks or layers if applicable, verification closure and the decision gate between another MPW and a dedicated run.
Use first-silicon evidence to decide on ECO, another prototype or a dedicated engineering route, then define qualification, test, supply, quality and commercial gates.
Public first contact is non-confidential. Do not send GDS, OASIS, RTL, netlists, schematics, PDK files or proprietary IP until the controlled NDA/data path is confirmed.
Preguntas que hacen equipos de ingeniería y procurement antes de enviar un brief.
Empiece con un brief no confidencial sobre nodo/proceso, calendario, validación del primer silicio, encapsulado/pruebas, manejo de muestras o re-spin. MST encamina la solicitud para revisión; la viabilidad, disponibilidad, plazos y cotización se confirman caso por caso.