Estimate gross dies per wafer, shared-reticle utilization, an indicative mature-node cost range, shuttle timing and tapeout readiness — before you have a finalized GDS. Planning intuition only; real availability and pricing are partner-confirmed.
Inputs
200 mm300 mm
Estimate
Die area
—
Gross dies / wafer
—
incl. edge exclusion + scribe
Shared-reticle share
—
of a typical multi-project reticle field
Indicative cost range
—
public-reference · partner-confirmed
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Tapeout readiness checklist
Node + process family confirmed (PDK access path identified)
NDA path agreed before any confidential design data is exchanged
Die area + I/O ring + seal ring + scribe rules respected
DRC / LVS clean against the chosen PDK before submission freeze
How this is calculated. Gross die per wafer uses the standard wafer-area / die-area model with edge exclusion and scribe: DPW ≈ π·(R²)/S − π·D/√(2S), where D is the usable diameter (wafer Ø − 2× edge exclusion), R = D/2, and S is the die area including scribe. Real net yield is lower (defects, partial dies, test). Shared-reticle share assumes a typical multi-project reticle field; actual reticle floorplan and cost-share are set by the partner. The indicative cost range is a coarse public-reference band for planning intuition only — it is not a quote, names no foundry, and varies widely by partner, mask set, options, package and test. Real pricing, availability, PDK access and schedule are confirmed case-by-case after review. MST is an MPW aggregation / RFQ coordination partner, not a wafer foundry.