Where Can I Manufacture a Small Batch of Custom Chips?
Compare MPW, prototype, multi-level-mask and dedicated-wafer routes for small-batch ASICs, including process fit, delivery form, packaging and test.
Short answer: A small batch of custom chips can be manufactured through a multi-project wafer (MPW) provider, a prototype or mini@sic program, a multi-level-mask route, or a dedicated wafer engagement. The right route depends on whether you need proof-of-silicon or repeatable supply, which process devices and PDK you need, your die area, the required delivery form, and who will own probe, dicing, packaging and test. Do not choose from a public calendar alone: first obtain a preliminary process and delivery-route fit, then ask the provider to confirm eligibility, current capacity, quotation and milestones.
The phrase “small batch” hides several different jobs. One team needs forty loose die to validate an analog front end. Another needs five hundred packaged engineering samples for customer trials. A third needs a repeatable low-volume supply for an industrial controller. Those projects can share the same circuit concept but require different manufacturing, commercial and quality routes.
Start with the result you need, not the wafer program name
Before contacting a provider, write a one-page non-confidential requirement. State the chip function, process-relevant electrical limits, expected die-size range, target sample quantity, delivery form, timing need and the evidence required at delivery. “We need a small run” is not enough to distinguish shared-wafer prototyping from a dedicated production route.
| Route | Best preliminary fit | Commercial unit | Typical limitation to resolve | Evidence before commitment |
|---|---|---|---|---|
| MPW shuttle | First silicon or design learning where several designs share mask and wafer cost. | Allocated design area, block or project, often with an included sample convention. | Fixed process option and run milestones; sample form and quantity vary. | Written process/option, registration and final-data deadlines, price basis, included deliverable and provider confirmation. |
| Prototype or mini@sic | Very small design or limited prototype access when the program and customer are eligible. | Smaller block or minimum area than a standard MPW offer. | Eligibility can be restricted; published availability is not universal commercial access. | Eligibility decision, participation terms, PDK route, minimum area and included samples. |
| Multi-level mask (MLM) | A process family supports multiple mask levels on one reticle and the economics suit the design. | Provider-specific mask/wafer arrangement. | Not offered for every process or design; technical restrictions must come from the provider. | Current process rules, mask configuration, wafer quantity, schedule and change boundary. |
| Dedicated wafer or full-mask set | Higher sample volume, repeatability, configuration control or production transition matters more than shared-run economics. | Mask/NRE plus wafer lots and downstream services. | Higher commitment and more complete manufacturing readiness. | Foundry or provider quote, mask ownership terms, lot plan, probe/package/test plan and re-order path. |
Important: MPW is not automatically the cheapest route for every “small” batch. Minimum billable area, included die, packaging, test development, logistics, re-spin probability and the next production step all affect total cost. A low fabrication line item can still produce an expensive unusable result if the delivery form is wrong.
Translate “a few chips” into a delivery specification
Ask what must physically arrive. A processed wafer, sawn wafer, loose bare die, bumped die, packaged engineering samples and electrically tested units are different deliverables. “One hundred chips” does not say whether the quantity is gross die, expected good die, packaged units or passing final-test units. Yield and final quantity cannot be guaranteed from an early public intake.
- Wafer: useful when your team or partner owns probe, dicing and assembly.
- Loose die: requires handling, identification, storage and an assembly or board-level plan.
- Packaged samples: require a frozen pad or bump map, package choice, substrate or leadframe feasibility and assembly instructions.
- Tested samples: additionally require test coverage, fixtures or load boards, test program ownership, limits and data reporting.
- Qualified product: requires a separate reliability and qualification plan; a working prototype is not a qualified production part.
The first engineering screen: process family before node
Do not begin with “Which 55 nm run is available?” Begin with the devices and models the circuit needs. A high-voltage power-management ASIC may need BCD devices and isolation. A nonvolatile controller may need an embedded-flash option and programming flow. A high-frequency front end may need SiGe HBT devices, while a digital accelerator may be driven by logic density, libraries and power-performance-area.
Then examine voltage domains, temperature, analog precision, RF targets, memory, IO, ESD, reliability, metal stack, passive devices and IP availability. The node label alone does not prove any of these. Final selection is subject to the actual PDK, design rules, model coverage and provider review.
A decision record that prevents expensive ambiguity
| Decision input | Evidence you need | Unknown owner | Next gate |
|---|---|---|---|
| Prototype learning or repeatable supply? | Named use case, next quantity step and acceptable re-spin plan. | Product owner | Select shared or dedicated route family. |
| Required devices and operating envelope | Voltage, temperature, frequency, precision, memory, IO and reliability ranges. | Chip architect | Preliminary process-family fit. |
| PDK and tool readiness | PDK access path, version, supported EDA flow, IP/library list and signoff decks. | Design lead/provider | NDA, eligibility and implementation plan. |
| Die area and geometry | Area estimate including IO, seal ring and provider margins. | Physical-design lead | Price basis and run registration. |
| Delivery form and quantity | Wafer/die/package/test definition and whether quantities are gross or tested-good. | Packaging/test owner | Downstream feasibility and quotation. |
| Schedule meaning | Exact timezone and definitions for registration, final data, tapeout and estimated shipment. | Provider | Written current-run confirmation. |
What public schedules and price tables do—and do not—prove
Public MPW pages are useful for building a shortlist. For example, the 2026 EUROPRACTICE tables distinguish standard and discounted pricing, identify whether a date is a registration or GDS deadline, and publish route-specific minimum-area notes. Other programs publish different milestones and sample conventions. These details show why a number copied without its currency, unit, minimum charge, eligibility class, included deliverable and source date is not a usable project price.
A schedule row does not prove that capacity remains, that your entity is eligible, that export-control review is complete, or that your design fits the named option. Treat it as dated evidence for a preliminary fit. Availability, slot, quotation, PDK access and dates remain provider-confirmed.
What to send in a safe first request
A first route review should contain only non-confidential screening information: application class, process-relevant ranges, preferred node or process family if known, estimated area, design status, target quantity, delivery form, desired timing, organization country and contact information. It should explicitly mark unknowns.
Do not put GDS/OASIS, RTL, netlists, schematics, layouts, screenshots, PDK files, rule decks, proprietary IP details or credentials into a public form. Confidential design exchange belongs in a separately authorized environment after identity, NDA, eligibility and responsibility boundaries are established.
Use the MPW Readiness Checker to structure a local non-confidential brief, then review the broader MST MPW access guide. For the account and onboarding path, read How to Tape Out Your First ASIC Without a Foundry Account. For choosing among public runs, read How to Choose an MPW Shuttle Run. Match the process family with BCD vs eFlash vs Logic CMOS vs SiGe BiCMOS. For downstream work, see Small-Batch Chip Manufacturing: Process, PDK, Packaging and Test and the existing MPW vs Full Mask comparison.
Request a non-confidential small-batch manufacturing-route review. MST can screen the stated requirement and coordinate a reviewed RFQ path; the relevant provider confirms technical acceptance, capacity, commercial terms and manufacturing milestones.
Frequently asked questions
Can a startup manufacture only a few custom chips?
Yes, some MPW and prototype programs are designed to reduce the first fabrication commitment by sharing a run or offering a small allocation. The workable route still depends on process fit, eligibility, minimum area, design readiness and whether “a few chips” means loose die or packaged and tested units.
Do I need a full wafer for a prototype ASIC?
Not always. A shared MPW program can provide an allocated area and a defined sample delivery without the customer buying a dedicated wafer lot. Confirm the exact delivery form, sample convention and what downstream work is excluded.
Is MPW always cheaper than a dedicated run?
No. MPW often reduces the initial fabrication commitment, but total project cost includes minimum billable area, design enablement, IP, packaging, test, logistics and possible re-spin. Dedicated routes can become more suitable when quantity, control or repeatability dominates.
Can I order packaged chips directly from an MPW schedule?
A public schedule by itself is not an orderable packaged-part specification. You must confirm whether the offer includes wafers, diced samples or another form, then separately align package feasibility, assembly inputs, test ownership and acceptance criteria.
How early should I contact a provider?
Before final layout. Eligibility, NDA/PDK access, process option, area reservation, commercial approval and downstream package/test decisions can precede final GDS by weeks or months. A dated registration milestone may occur before the final-data deadline.
Primary sources and review boundary
- EUROPRACTICE 2026 schedules and prices — current public examples of run dates, eligibility classes, price units, minimum-area rules and sample notes.
- GlobalFoundries GlobalShuttle — an official description of shared-wafer prototyping and sample flexibility.
- imec IC-Link 2026 MPW schedules — provider-run schedules with process-specific milestone fields.
- IHP MPW and prototyping service — an official example of research/prototyping access, design flow and delivery conditions.
- Amkor services — downstream package, assembly and test capabilities that must be scoped separately from fabrication.
Last technically reviewed: July 30, 2026. This is an engineering route guide, not a quotation or manufacturing commitment. Program eligibility, PDK access, process options, capacity, prices, milestones and delivery definitions change and require current written confirmation.
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Ready to plan your MPW and first-silicon path?
Start with a non-confidential brief covering node/process fit, schedule, first-silicon validation, packaging/test, sample handling or re-spin needs. MST routes the request for review; feasibility, availability, timing and quotation are confirmed case by case.