HHGrace MPW 55nm, 90nm & 40nm Process Fit
Screen HHGrace 55nm, 90nm and 40nm candidates by devices, voltage, eFlash, BCD, RF, IP and reliability before fab review.
Short answer: Do not select an HHGrace (Hua Hong / 华虹) MPW route from “55nm,” “90nm” or “40nm” alone. Start with the circuit’s device, voltage, memory, RF/analog, reliability, IP and package/test requirements. Hua Hong’s 2025 public filing describes company-platform progress including 55nm eFlash mass production, 40nm eFlash risk production, stable 90nm BCD mass production and 55/40nm specialty and RF CMOS production. Those statements support an initial process-family discussion; they do not prove that an MPW option, PDK, capacity or project acceptance is available. MST coordinates a fab review of the exact requirement.
The buyer’s real question is not “Which node is best?” It is “Which fab-confirmed process option can implement this product with the required devices, models, IP, reliability and delivery path?” A smaller node can be a worse fit when embedded memory, high-voltage devices, RF passives, temperature range, isolation or trusted IP is the controlling constraint.
What the public evidence can and cannot tell you
Public Hua Hong information is useful for establishing that the company operates multiple mature-node and specialty-technology families. The 2025 annual report describes specific platform status at company level. The HHGrace customer-inquiry form asks prospects to identify application market, end product, chip type and platform. Together, those sources show why the enquiry must start with product requirements and a platform hypothesis.
They do not establish a shuttle code, current MPW opening, the precise device menu, the applicable PDK revision or eligibility for an overseas customer. In particular, a request for SiGe BiCMOS should be recorded as a requirement to be confirmed by the fab; this article does not claim a current HHGrace SiGe MPW offering.
Screen the process family before the node
| Requirement family | Questions to state | Evidence needed next | Common false shortcut |
|---|---|---|---|
| Logic / ultra-low power | Performance target, leakage, core/IO voltage, memory, power modes and library needs. | Exact process option, device list, PDK/library versions and characterized corners. | Assuming all 40nm or 55nm logic options are interchangeable. |
| Embedded flash | Memory density, endurance, retention, programming voltage, security and automotive/industrial context. | Applicable eFlash option, qualified IP, reliability conditions and availability for review. | Converting a public platform-status statement into an MPW offer. |
| BCD / power management | Voltage domains, SOA, isolation, power devices, analog precision, thermal and protection needs. | Device and isolation menu, models, layout rules, reliability targets and package constraints. | Selecting 90nm because the digital portion fits while ignoring high-voltage devices. |
| RF / mixed signal | Frequency, noise, linearity, passives, substrate isolation, IO and package parasitics. | RF device/passive models, stack, measured model range and package co-design assumptions. | Using nominal node as a proxy for RF performance. |
| SiGe BiCMOS request | Frequency, gain, noise, breakdown, passive and temperature requirements. | Fab confirmation that a suitable controlled option and access route exist. | Assuming a generic RF statement proves SiGe availability. |
How to compare 90nm, 55nm and 40nm without overclaiming
Use the node as an index into a requirements review, not as the conclusion. At 90nm, a power-management or embedded-memory need may dominate; at 55nm, embedded flash, analog/power or specialty logic may be the reason to investigate; at 40nm, density or low-power logic may matter. But the available device set, IO voltage, metal stack, memory compiler, IP, reliability flow and customer access remain specific to the exact fab option.
For each candidate, create a requirement-to-evidence matrix. Mark every item as documented, fab-confirmed, inferred or unknown. Any hard requirement that remains unknown blocks selection. A preliminary match is valuable—it narrows the next conversation—but it is not a signoff decision.
| Decision input | Evidence required | Unknown owner | Next gate |
|---|---|---|---|
| Functional partition | Digital, memory, analog, power and RF block requirements with priorities. | System/chip architect | Process-family shortlist. |
| Voltage and device set | Core/IO domains, high-voltage devices, isolation, passives and ESD assumptions. | Analog/power lead | Fab device-menu review. |
| Memory and IP | eFlash or other NVM need, SRAM/ROM, libraries, interface IP and qualification status. | IP owner | Controlled availability check. |
| RF performance | Frequency band, NF, linearity, power, passives and package model needs. | RF lead | Model and package-fit review. |
| Reliability | Temperature, lifetime, endurance, retention, automotive/industrial requirements. | Quality/reliability owner | Applicable flow confirmation. |
| MPW route | Customer eligibility, PDK path, die range, readiness and current fab review outcome. | MST/fab coordinator | Fab-confirmed project route. |
What to send in the first non-confidential brief
- Product and end use: identify the application, operating environment and customer entity/country.
- Hard electrical constraints: state voltages, performance, memory, RF and temperature requirements without attaching proprietary schematics.
- Process hypothesis: list preferred and acceptable node/process families and explain why.
- Implementation assumptions: give die-area range, major IP/library dependencies, EDA environment and signoff readiness.
- Delivery assumptions: give sample form, package/test need and target timing as planning inputs.
MST can screen the completeness of that brief and coordinate the HHGrace review. The fab remains responsible for deciding whether a particular process option, PDK path and project is technically and commercially eligible.
Avoid keyword-driven process selection
- “55nm eFlash” is not a full specification; memory size, endurance, voltage, IP and reliability still matter.
- “90nm BCD” does not state the required high-voltage device, SOA, isolation or analog model quality.
- “40nm low power” does not prove a compatible IO, memory compiler, IP set or MPW path.
- “RF” is not the same as “SiGe BiCMOS”; record SiGe as an explicit requirement requiring fab confirmation.
- A company-level production statement is not evidence of capacity or a shuttle opening for one project.
Use the right supporting resources
Start at the HHGrace MPW agent entry for a fab-facing enquiry. Use the localized MPW Node Selection Advisor to structure a first shortlist before asking the fab to confirm an exact option.
Frequently asked questions
Does Hua Hong’s 2025 report mean 55nm eFlash is available on MPW?
No. The filing describes company-platform status. It does not state a current MPW opening, eligibility, PDK release, capacity or acceptance for a particular overseas design.
Is 90nm always the right node for BCD?
No. The required voltage, SOA, isolation, device menu, analog performance, embedded memory, reliability and package determine fit. The node label only starts the review.
Can MST confirm an HHGrace SiGe BiCMOS route?
MST can record and route the SiGe requirement for review. This page does not assert that a current suitable HHGrace SiGe MPW option exists; the fab must confirm the exact route.
What blocks process selection most often?
Unstated voltage domains, missing memory/endurance requirements, assumed IP availability, incomplete RF/package constraints and treating a public platform name as the applicable PDK option are common blockers.
Can I screen process fit without sharing design IP?
Yes. Start with functional requirements, voltage, memory, RF, reliability, die range, EDA context and schedule assumptions. Controlled design information belongs in a later approved exchange path.
Primary sources and review boundary
- Hua Hong Semiconductor 2025 Annual Report — public company-platform status for 55nm/40nm eFlash, 90nm BCD and specialty/RF CMOS context.
- Hua Hong Group technology overview — official public specialty-technology family context.
- HHGrace Customer Inquiry — official initial fields for application market, end product, chip type and platform.
- HHGrace Online FAQ — official customer-support context.
- SMIC Technology Platform — an official alternative-provider example showing that nodes are organized with process platforms; it is not evidence about HHGrace availability.
Last technically reviewed: August 9, 2026. Public process statements are discovery evidence, not an MPW offer. Exact platform fit, PDK, customer eligibility, capacity, schedule, quotation and order acceptance remain fab-confirmed case by case.
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Ready to plan your MPW and first-silicon path?
Start with a non-confidential brief covering node/process fit, schedule, first-silicon validation, packaging/test, sample handling or re-spin needs. MST routes the request for review; feasibility, availability, timing and quotation are confirmed case by case.