MPW

GDSII, DRC and LVS Requirements for MPW Tapeout

What MPW teams should prepare before layout handoff: top cell, layer map, DRC/LVS status, waivers, pad ring, package context and manifest.

GDSII layout, DRC and LVS verification panels, layer map and wafer reticle for MPW tapeout readiness
Key Takeaways
  • What is GDSII in tapeout?
  • Core readiness fields
  • DRC and LVS are not optional paperwork
  • What to submit before NDA
  • Use local tools before sharing files

Answer block: MPW tapeout readiness usually requires more than a GDSII file. Teams should prepare the correct top cell, layer map, DRC/LVS status, waiver list, pad ring assumptions, package context, checksum and a clear handoff manifest. MST recommends sharing only non-confidential readiness information at intake, then moving to NDA and partner-confirmed review before any layout data is exchanged.

Searches for “GDSII requirements for tapeout” often come from teams that are close to first silicon but unsure what a foundry or shuttle coordinator will ask for. The answer depends on process and partner route, but the structure of a clean handoff is consistent.

What is GDSII in tapeout?

GDSII is a layout exchange format used to represent chip geometry. It is not the complete story. A partner must know which top cell to use, which process and layer mapping apply, what signoff checks were run, and whether any rule waivers or known issues exist.

Core readiness fields

  • Top cell: exact cell name and hierarchy expectation.
  • Process and node: foundry/process option or candidate range.
  • Layer map: process-specific mapping, not a guessed generic layer list.
  • DRC: run date, deck version, clean status and waiver list.
  • LVS: netlist source, run date, clean status and known exceptions.
  • Pad ring and IO: pad count, ESD assumptions, power domains and package implications.
  • Manifest: file names, checksums, owner, date and revision.

DRC and LVS are not optional paperwork

Design Rule Check confirms that physical geometry follows process rules. Layout Versus Schematic confirms that the layout matches the intended circuit connectivity. A clean visual layout can still fail DRC or LVS, and a passed local flow may still need partner review if the wrong deck, wrong process option or incomplete waiver policy was used.

What to submit before NDA

Before NDA, do not submit GDS, schematics, RTL, netlists or proprietary IP. Submit only high-level readiness fields: node range, process family, estimated die area, current DRC/LVS status, package/test assumptions and timeline. That is enough to screen whether a route may fit.

Use local tools before sharing files

MST publishes a Local GDSII Inspector for browser-side file inspection. It is designed for non-confidential planning: checking basic structure, hierarchy and metadata locally before any partner handoff. It is not a replacement for foundry signoff.

FAQ

Can an MPW RFQ start before DRC/LVS is clean?

Yes, for route screening. But final tapeout requires partner-specific readiness and signoff discipline.

Should I email GDS to get a price?

No. Start with non-confidential requirements. Layout data should be exchanged only through an approved path after NDA and route confirmation.

What is a tapeout manifest?

A tapeout manifest is a structured handoff record listing files, process assumptions, top cell, checksums, signoff status and known exceptions.

For broader context, read How to Tapeout a Chip: First Silicon Checklist and the MPW shuttle guide.

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