Use only non-confidential first-screen information. Approximate values are enough.
Target node Select node 0.35um / 350nm 0.18um / 180nm 130nm 90nm 65/55nm 40nm 28nm case-by-case Not sure yet
Process family Select process Analog mixed-signal CMOS BCD / power management High-voltage RF / RFIC eNVM / eFlash MEMS / sensor Logic CMOS Not sure yet
Design stage Select stage Concept / architecture Schematic in progress Layout in progress DRC/LVS cleanup Ready for partner review after NDA
PDK access status Select PDK status PDK access requested PDK under NDA discussion Public/open PDK used for prototype Need PDK path guidance Not started
DRC/LVS status Select signoff status DRC clean, LVS cleanup in progress DRC/LVS cleanup in progress Known violations under review Signoff responsibility not assigned Not started
Handoff format Select handoff path GDS/OASIS after NDA only Handoff manifest after NDA Need handoff checklist No layout handoff yet
Package plan Select package plan QFN likely, recommendation needed LQFP likely, recommendation needed BGA / WLCSP likely COB / bare die acceptable Customer-specified package Not decided
Probe / test plan Select test plan Wafer probe and basic packaged test needed Wafer probe needed Packaged test needed Customer handles test Not decided
