FPGA to ASIC: When a Prototype Should Move Toward MPW
How founders and engineering managers can decide whether FPGA, MPW or a dedicated ASIC route fits the product stage.
- →What engineers should clarify first
- →MPW is not an FPGA replacement by itself
- →Cost is more than wafer share
- →A staged brief is safer than a GDS upload
- →How this connects to MST
Answer-first summary: Moving from FPGA to ASIC is justified when unit economics, power, latency, form factor, IP protection or product differentiation outweigh the extra NRE and verification burden. MPW is often the bridge between a working FPGA prototype and a dedicated production route.
Many teams search for MPW before they know they are searching for MPW. The actual question is whether the product has outgrown FPGA. MPW becomes relevant when the team needs silicon learning without committing immediately to a full dedicated mask set.
What engineers should clarify first
| Signal | Stay FPGA | Consider MPW / ASIC |
|---|---|---|
| Volume | Low volume or changing product | Volume large enough for unit economics and power efficiency to matter |
| Power / latency | FPGA budget acceptable | Power, latency or form factor blocks product requirements |
| Design maturity | Architecture still changing weekly | Architecture stable enough for silicon validation |
| Capital risk | No budget for signoff/test | Budget exists for verification, package and post-silicon work |
MPW is not an FPGA replacement by itself
An MPW shuttle gives first silicon data. It does not replace RTL verification, DFT, package planning, test strategy or software/firmware bring-up.
Cost is more than wafer share
Teams should estimate EDA tools, IP, verification, package, board, test, characterization and engineering time. The wafer or shuttle fee is only one line item.
A staged brief is safer than a GDS upload
A startup can ask whether MPW is plausible by sharing architecture level, node family, die-area estimate, IO/package needs and timeline without sending design IP first.
How this connects to MST
Send a high-level FPGA-to-ASIC readiness brief before preparing confidential design files. MST uses this article as an intake guide, not as a promise of partner access, compliance certification, fixed sample count, fixed pricing, or automatic production approval.
FAQ
Is MPW good for a first ASIC?
Often yes if the design goal is learning and validation. It is not a shortcut around verification.
Can I ask for cost before I have GDS?
Yes. A high-level cost read can start with node, process family, die area, package/test direction and schedule.
What if my FPGA architecture is still changing?
Keep iterating on FPGA until the silicon learning goal is stable enough to justify tapeout risk.
Public references for engineering context
Ready to scope your run?
Send node, process family, die area, volume and timeline - no design IP. We screen it, route to a qualified partner, and return an indicative quote.